Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple layers of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, incorporated by reference herein.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009, incorporated by reference herein. The structure described in Katsumata et al. includes a vertical NAND gate, using dielectric charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a gate-all-around cell at each layer.
FIG. 1 and FIG. 2 are respectively a top view and a side view of a pipe-shaped column of flash cells. Referring to the top view in FIG. 1, a bit line (hashed outline 8) is connected to an interlayer conductor 9, which in turn contacts a contact pad 10 on top of a vertical channel pillar 15. The contact pad 10 in this illustration obscures the core of the vertical channel pillar 15, but shows in cross section the dielectric charge trapping structure comprising for example a first layer 16 of silicon oxide, a layer 17 of silicon nitride and a second layer 18 of silicon oxide (referred to as ONO), or another multilayer dielectric charge trapping structure, which surrounds the cylindrical shell 14 of semiconductor material. The pillar 15 is characterized by a cell diameter “a” which is the outer diameter of the outer second layer 18 of the dielectric charge trapping structure of the pillar 15. In the top view of FIG. 1, a string select strip 24 is shown contacting the outer second layer 18 of the dielectric charge trapping structure. A string select gate is thus established for the pillar.
Referring to the side view in FIG. 2, the contact pad 10 overlies the core of the pillar 15, including a cylindrical shell 14 of semiconductor material. The cylindrical shell 14 of semiconductor material extends vertically through layers of conductive strips, including the string select strip 24, a multilevel stack of conductive strips configured as word line conductive strips 20-23, and ground select strip 25 in the bottom layer. The cylindrical shell 14 of conductive semiconductor material has an insulating core 11 inside in this example. Alternatively the core inside the cylindrical shell has metal material. Alternatively the conductive semiconductor material is a solid cylinder of semiconductor material. The dielectric charge trapping structure comprising for example a first layer 16 of silicon oxide, a layer 17 of silicon nitride and a second layer 18 of silicon oxide (referred to as ONO), or another multilayer dielectric charge trapping structure, surrounds the cylindrical shell 14 of semiconductor material. The pillar 15 is characterized by a cell diameter “a” which is the outer diameter of the outer dielectric of the pillar 15. The outer second layer 18 of the dielectric charge trapping structure is in contact with the conductive layers 20-23 configured as word lines, resulting in memory cells at the cross points. The bottom conductive strip 25 configured as a ground select line also contacts the outer second layer 18 of the dielectric charge trapping structure in this example. In some embodiments, the dielectric between one or both of the string select strip 24 and the ground select strip 25 is different than the dielectric charge trapping structure.
As illustrated in the top view of FIG. 1, string select line SSL strip 24 is intersected by the pillar 15, such that string select line SSL strip 24 is an all-around gate. Below the string select line SSL strip 24, layers of word line strips WLs 20-23 are each intersected by the pillar 15, each also an all-around gate. A frustum of the pillar 15 combines with each of the word lines WLs 20-23 to form a memory cell at each layer. Below the word lines WLs 20-23 ground select line GSL 25 also is intersected by pillar 15.
Accordingly, a NAND string is formed on the current path through the cylinder of semiconductor material, between the bit line conductor BL 8 and the ground GND below the cylinder of semiconductor material (not shown).
FIG. 3 is a perspective view of a 3D semiconductor device. It comprises a multilevel stack of word line conductive strips 20-23 over a substrate (not shown); a plurality of pillars 15 extends through the stack, each of the pillars 15 comprising channels of a plurality of series-connected memory cells located at cross-points between the pillars 15 and the word line conductive layers 20-23 and a plurality of string select lines (SSLs) 24 in a string select line layer above the word line conductive layers 20-23, each of the string select lines intersecting a respective row of the pillars 15. Each intersection of a pillar 15 and a string select line 24 defines a string select gate (SSG) of the pillar. The structure also includes ground select lines GSL strip 25A, 25B oriented parallel to the substrate and forming a layer below the word line conductive layers 20-23. A common source line (CSL) 27 is formed in a layer parallel to the substrate and below the GSLs 25A, 25B. Each intersection of a pillar 15 and a ground select line 25 defines a ground select gate (GSG) of the pillar. The pillars in the plurality of pillars that share GSL line 25A can be coupled to the common source line 27, and therefore selected for operation using the GSL strip 25A. Likewise, the pillars in the plurality of pillars that share GSL line 25B can be coupled to the common source line 27, and therefore selected for operation using the GSL strip 25B. The structure also includes a plurality of parallel bit line conductors 8 in a layer parallel to the substrate and above the string select lines 24. Each of the bit line conductors 8 overlies a respective column of the pillars 15, and each of the pillars 15 underlies one of the bit line conductors 8. The pillars 15 may be constructed as described above with respect to FIGS. 1 and 2. The group of pillars, coupled to a single SSL line in this configuration, is arranged in a line perpendicular to the bit line direction, and includes one pillar per bit line, and each bit line is coupled to one pillar in each group of pillars.
As shown in FIG. 3, a typical arrangement has a stepped contact structure to the word line conductive layers. Deep etches are made through the structure in order to form contacts to connect the conductive layers to metal interconnects above. In a typical design, the number of rows of pillars in a block is at least as great as the number of contacts, and hence memory layers. See, for example, Komori, Y., et al., “Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device,” IEEE Int'l Electron Devices Meeting, pp. 1-4, 15-17 Dec. 2008, incorporated herein by reference.
The layout of the memory structure therefore can expand with the overhead of connections to the stacks of conductors, and the relatively large diameter of the vertical channel pillars. This large overhead is a limit on bit density in 3D memory.
An opportunity therefore arises to create robust solutions to the problem of increasing bit density of 3D memory structures while reducing the negative impacts that such increases tend to cause. Better chip yields, and denser, and more powerful circuits, components and systems may result.